1. Field of the Invention
The invention relates to a data processing apparatus, comprising an addressing arrangement for supplying a memory with address codes originating from a variable-content principal register to which are connected an incrementation circuit for modifying the content of the principal register and a loading circuit. The addressing arrangement comprises two auxiliary registers, one of which serves to store the minimum value to be reached by the content of the principal register while the other auxiliary register serves to store the maximum value to be reached by the principal register. A comparison circuit determines when the content of the principal register reaches the minimum and maximum values.
2. Description of the Related Art
Such a apparatus is widely used, notably for performing the functions of a fixed or adaptive transversal data transmission filter. At successive addresses the memory contains different samples in digital form of the signal to be filtered. For processing of the signal it is necessary to address the memory locations containing these samples cyclically, so as to simulate a shift register in RAM-type memory.
Apparatus of the kind set forth is described in the article "An LSI Signal Processor" by M. Yano, K. Inoue and T. Senba in volume 2 of IEEE International Conference of Acoustics, Speech and Signal Processing, held in Paris, France on May 3, 4, 5, 1982.
In the known apparatus the comparison circuit compares the content of the principal register with that of the auxiliary register containing the maximum value. Consequently, the content of the principal register must always be modified in the same direction in practice.